Job Description
We are seeking a skilled and experienced SOC DFT Design Engineer to join our dynamic team. The ideal candidate will be responsible for developing and implementing DFT (Design for Test) solutions for complex system-on-chip (SOC) designs. You will work closely with cross-functional teams, including design, verification, and manufacturing, to ensure that our SOC products meet the highest quality standards and are testable in the most efficient manner. Key Responsibilities: DFT Architecture and Implementation: Design and implement comprehensive DFT solutions for SOCs, including scan insertion, boundary scan, built-in self-test (BIST), and memory test solutions. Work closely with the design and verification teams to integrate DFT techniques into SOC design flows. Specify and implement various test methodologies, including scan chains, JTAG, ATPG (Automatic Test Pattern Generation), and fault simulation. Support the integration of advanced test features like power-on reset testing, JTAG, and functional tests. Test Coverage and Validation: Optimize test coverage to ensure complete validation of the SOC's functionality. Work with verification engineers to define test patterns and ensure that all logic in the SOC is thoroughly tested. Perform post-silicon validation to ensure that DFT features work as expected. Automation and Tools: Develop scripts and automation tools to streamline DFT-related processes, including scan insertion, ATPG, and fault simulation. Collaborate with EDA tool vendors to ensure compatibility and best practices for DFT toolchain integration. Analyze and provide feedback on DFT tools, and contribute to improvements in testability. Collaboration and Support: Work closely with the SOC design and validation teams to troubleshoot and resolve DFT-related issues during the design, simulation, and testing phases. Assist in the development and execution of DFT strategy documentation and design guidelines. Provide technical support for manufacturing test, including support for yield analysis, failure analysis, and root-cause diagnosis.
Qualifications

Education:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Experience:

3+ years of experience in SOC design, DFT, or related fields.Solid understanding of digital design and experience with ASIC/SOC design flows.Hands-on experience with DFT methodologies, including scan insertion, boundary scan, BIST, and memory testing.Experience with industry-standard tools like Synopsys DFT tools (e.g., DFT Compiler, TetraMAX) or Mentor Graphics tools (e.g., Tessent).Familiarity with the JTAG and IEEE 1149.1 standard.Proficient in scripting languages (e.g., TCL, Perl, Python) to automate design flows and tests.

Skills and Competencies:

Strong problem-solving skills and the ability to troubleshoot complex design issues.Knowledge of SOC architecture, RTL design, and verification methodologies.Excellent communication skills and the ability to work effectively in a collaborative, cross-functional team.Detail-oriented with strong analytical and debugging skills.

Desirable Skills:

Experience in pre-silicon verification or post-silicon validation.Familiarity with advanced test techniques like Logic BIST, Memory BIST, and Analog/Mixed-Signal testing.Knowledge of fault models and fault simulation for functional and structural testing.Experience with FPGA-based prototyping and emulation for SOC testing
Inside this Business Group
The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Other Locations

MY, Kulim


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.