SoC Physical Design Engineer, Top Level Beaverton,Oregon,United States Hardware Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout. **Description** • Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. • Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution **Minimum Qualifications** + Minimum BS and 10+ years of relevant industry experience. + Need to be familiar with aspects of ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration. + Experience with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions. + Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain is required. + A detailed understanding of database management issues is required. + From a CAD tool perspective, experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows is required. **Key Qualifications** **Preferred Qualifications** + Familiar with a hierarchical design approach, top-down design, budgeting, timing and physical convergence. + Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using innovative sub 7nm technologies. + Familiar with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies, and thermal Mgt. **Education & Experience** Minimum BS and 10+ years of relevant industry experience **Additional Requirements** + Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) **Apple Footer** Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) . Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) . Apple will consider for employment all qualified applicants with criminal histories in a manner consistent with applicable law. If you’re applying for a position in San Francisco, review the San Francisco Fair Chance Ordinance guidelines (opens in a new window) applicable in your area. Apple participates in the E-Verify program in certain locations as required by law. Learn more about the E-Verify program (Opens in a new window) . Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) . Apple is a drug-free workplace. Reasonable Accommodation and Drug Free Workplace policy Learn more (Opens in a new window) .