At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Successful applicant will participate in the design and development of a fully configurable and fully featured Network on Chip (NoC) product. Responsibilities include hardware architecture and micro-architecture definition, as well as RTL design to achieve high performance and low power. Familiarity with NoC technology and concepts, AMBA protocols (AXI, AHB, APB) as well as coherency protocols (ACE, CHI) required.

BSEE and at least 7 years of prior experience required. MSEE and at-least 5 years of prior experience strongly preferred.

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