L3Harris is dedicated to recruiting and developing diverse, high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers’ mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.

L3Harris Technologies is an agile global aerospace and defense technology innovator, delivering end-to-end solutions that meet customers’ mission-critical needs. The company provides advanced defense and commercial technologies across space, air, land, sea and cyber domains. L3Harris has approximately $18 billion in annual revenue and 50,000 employees, with customers in more than 100 countries.

Job Title: Sr. Semiconductor Advanced Packaging Designer (Cadence Allegro)

Job Code: 16822

Job Location:  Palm Bay, FL

Job Schedule: 9/80 (Every other Friday off!)

Relocation: Relocation assistance may be provided for qualified applicants

Job Description:

This role will require you to design complex die level component packages requiring knowledge of Silicon substrates, die stacking, TSVs and die attachment technologies. Designs will be captured using Cadence EDA tools including Advanced Package Designer (APD) and System Connectivity manager (SCM). Your primary responsibilities will require an understanding of advanced packaging technologies, packaging materials and material properties along with processes and an intimate knowledge of CAD SW and design verification tools. This position requires interface with the fabrication and assembly team with the opportunity to become more involved in these operations, designing interconnect test structures to enable chip-to-chip process development.

Essential Functions: 

Work closely with a small team to achieve and develop designs for multi die packages using Cadence APD (Advance Package designer 24.1) and Cadence SCM. Understand and apply design verification software (PVS, LVS), incorporate design data in a Wafer level design working with internal and external foundry engineers coordinating fabrication features such as targets, metallization plans and process flows.Candidate will be responsible for creating and maintaining schematics (Cadence SCM) and design databases (Cadence APD)Must be able to adapt to an evolving process and work closely with teammates providing up to date changes.Position will require individual to interface with other team members on tool development and process flow; as well as designing test structures for process development and integration. Manages complex interposer designs, works across multiple industry standard/non-standard die design CAD tools, develops processes, performs failure analysis investigations, RCCAs, and leads a team of designers.Create design process control documentation and mentor/lead other personnel on design rules and processes.Work with general oversight and lead technical team of up to 6 additional engineers and designers. Domestic and International Travel Required up to 25% of time

Qualifications:

Bachelor’s Degree and a minimum of 9 years of prior relevant experience or Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.Ability to obtain a Top Secret/SCI U.S. government Security Clearance Experience using Cadence Allegro Package Design suite5+ years experience with updating, operating, and designing with new semiconductor design CAD tools and processesPrior or current experience documenting, communicating, and presenting technical topics/recommendations/issues/concerns to internal and external customersExperience in advanced microelectronics packaging including through silicon vias, redistribution layers (RDL), chip stacking, and fan out

Preferred Additional Skills:

Active Top Secret/SCI clearance Ability to lead a design team, size 2-10 people.Experience using Cadence APD (Advance Package designer 24.1) and Cadence SCMExperience with silicon photonicsAutocad, L-Edit, Klayout, or equivalent 2D mask layout tool

Please be aware many of our positions require the ability to obtain a security clearance. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.

By submitting your résumé for this position, you understand and agree that L3Harris Technologies may share your résumé, as well as any other related personal information or documentation you provide, with its subsidiaries and affiliated companies for the purpose of considering you for other available positions.

L3Harris Technologies is proud to be an Affirmative Action/Equal Opportunity Employer. L3Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws. L3Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law.

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