Company:Qualcomm Semiconductor Limited

Job Area:Engineering Group, Engineering Group > ASICS Engineering

General Summary:

We are looking for talented and ambitious individuals to join the TECHIP team. The candidate should have strong IP modeling, Char tool know-how and hands-on experience and automation skills. Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation enablement.  Good understanding of statistical Liberty timing, power model and Front-end Verilog views and tools. Silicon reliability modeling, validation with multiple foundries & EDA house is a plus.

The ideal candidate would also have experience with industry standard chip design tools and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power Analysis.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Minimum Requirements:

Strong Std cell / Memory circuit knowledge & IP characterization , Design Kit delivery background.Strong logical and problem-solving skills with excellent analytical and debugging skillsStrong Software programming skills in Python or Perl in UNIX/Linux computing platformHighly motivated, excellent team spirit and good communication skills.Ability to work in multi-site project teams, third party vendors to drive cutting edge tools, flows in QCOM environment for characterization flow and sign-off methodologies

Preferred Qualifications:

In depth technical knowledge of CMOS, FinFET logic and transistor, basic of digital circuit design optimization Familiar with industry standard Design kit (DK) views, Liberty formats for foundation IPs (advanced modeling formats CCS, LVF) , statistical variation models & worked on development of the same.Familiarity with  front end pre-silicon design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience.Expertise in scripting in Python (data-analytics), Perl & experience in developing large scale automation from scratch.Experience in STA, physical design is a plus.Experience of spice simulation models, design rules verification procedures (like DRC/LVS/ERC) is a plus.

Education Qualifications

Required: Bachelors, Electrical Engineering or Computer Engineering or Computer SciencePreferred: Master's, Electrical Engineering or Computer Engineering or Computer Science

Work Experiences:

7 - 10 years Library characterization or Custom circuit design or CAD flow development or VLSI related work experience.

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