Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
What you will do:
Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST
Who you are:
You are an ASIC engineer with 8+ years of related work experience with a broad mix of technologies including:
10+ years of experience with deep domain knowledge in Static Timing Analysis and ECO generation. Must have experience in closing the STA at the block and full chip level with multiple hierarchies included. Synopsys PrimeTime, Tweaker , Prime Closure, ECO generation and design closure. STA and ECO generation using Cadence Tempus to help the design timing closure. Well versed with timing constraint development and validation. Knowledge of Parasitic Extraction Flow, Noise Delay and Glitch Analysis Flow. Deep understanding on aging and other derates. Able to contribute in developing the clock tuning methodologies to ease the chip level timing closure. Experience in PTPX of Power Analysis Flow. Proficient in software and scripting skills (Perl, Tcl, Python). Exceptional Debugging skills.Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team.
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