Join our esteemed CHG Team in Armenia, a leader in physical design and implementation for pioneering networking chips under the renowned Silicon One brand. Located in Armenia, our team is dedicated to achieving full chip timing closure, signoff, and ensuring high-quality circuit timing, all in preparation for tape-out.

Why You’ll Love Cisco

We change the World, you will become passionate about your employer and the brand you represent. Everything is converging on the Internet, making networked connections more meaningful than ever before in our lives. Our employees' groundbreaking ideas impact everything. Here, that means we take creative ideas from the drawing board to dynamic solutions that have real-world impact. You'll collaborate with Cisco leaders, partner with mentors, and develop incredible relationships with colleagues who share your interest in connecting the unconnected. You'll be in a team that cares about its customers, enjoys having fun, and you'll take part in changing the lives of those in our local communities. Come prepared to be encouraged and inspired.

What You'll DoPerform full-chip STA; review and debug issues; provide solutions; and ensure signoff clean results.Debug SDC issues and provide feedback to Front-End teamPerform full-chip timing ECO; deeply explore tool configurations and methodologies; refine and implement efficient strategies to ensure seamless timing ECO execution.Generate and provide manual ECOs for timing issues tool can’t handle automaticallyWork closely with block level PD teams to understand each block’s behavior and implementation challenges.Who You'll Work With

You will be part of the Silicon One development team in Armenia, concentrating on chip-level STA and closure. You will collaborate closely with block implementation teams, flow teams, SDC development teams, the EMIR team, tool vendors, and IP vendors. Our team is made up of forward-thinkers who are passionately driven by innovation, continuous learning, and collaboration.

Who You Are

If you are a skilled engineer with strong experience in physical verification, adept at debugging and providing solutions, and have a solid understanding of deep submicron CMOS technologies. You will thrive in our team that values collaboration and growing, fostering a supportive and innovative environment.

Minimum Qualifications:5+ years of experience in Static Timing Analysis, including expertise in debugging and developing effective solutions.Experience in deep submicron CMOS technologies relevant to process.Strong knowledge and experience in CMOS Digital Design Flow.Bachelor's or Master's degree in Electrical Engineering or Computer Science or any other relevant field.Excellent verbal and written communication skills in English.Preferred Qualifications:Understanding of the full physical design cycle from RTL to GDSII.Hands-on experience in STA and timing ECO.Knowledge of scripting languages (Tcl, Python, Shell).Why Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all.

We adopt digital and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take the difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward.

#WeAreCisco