Role Proficiency:

Execute any sized customer projects independently with minimum supervision. Guide team members technically in any field of VLSI Frontend Backend or Analog design

Outcomes:

     As an Individual contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff. etc.; leading the team to achieve results.      Complete assigned tasks successfully and on-time within the defined domain(s)      Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams      On time quality delivery approved by the project manager and client      Automate the design tasks flows and write scripts to generate reports      Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and Client      Write paper(s) file patent(s) and device new design approaches

Measures of Outcomes:

     Quality –verified using relevant metrics by UST Manager / Client Manager      Timely delivery - verified using relevant metrics by UST Manager / Client Manager      Reduction in cycle time and cost using innovative approaches      Number of papers published      Number of patents filed      Number of trainings presented to team

Outputs Expected:

Quality of the deliverables:

Bugs present in the design / circuit design. Zero bug is expected from the client Clean delivery of the design/module in-terms of ease in integration at the top level Meeting functional spec / design guidelines 100% without any deviation or limitation Documentation of the tasks and work performed

Timely delivery:

Meeting project timelines as laid out by the client or program manager Meeting intermediate tasks delivery facilitating other team members to progress Calling out for help and support in-case of delay in tasks delivery on a case to case basis

Team Work:

Participation in team work and supporting team members at the time of need Anticipate when team may need support and discuss with project manager to resolve issues Able to hand hold junior team members to explain the project tasks and support delivery

Innovation & Creativity:

Automating tasks to save design cycle time on repetitive work processes Participation in technical discussion
training
forum
white paper or patent filing

Skill Examples:

     Languages and Programming skills:a.     System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice      EDA Tools: a.     Cadence Synopsys Mentor tool sets (one or more)b.     Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience with one or more tools)      Technical Knowledge:a.     Implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb.     Understand and implement Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec.      Strong Physical Design / Circuit Design / Analog Layout Knowledged.     Strong Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione.     Strong Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design      Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below      Strong communication skills and ability to interact with team members and clients equally      Strong analytical reasoning and problem-solving skills with attention to details      Well versed and able to efficiently use the available EDA Ability to deliver the tasks on-time per quality guidelines and GANTT      Ability to understand the standard specs and functional documents      Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project

Knowledge Examples:

     Have led and executed project(s) in any of the design by executing – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.      Understanding of the design flow and methodologies used in designing Understanding of the assigned tasks and a good knowledge to execute the project tasks assigned by the client / manager as per known skills

Additional Comments:

Experience: 5- 10 Years Desired Skills and Experience: • Engineers is expected to be very good in Basic Fundamentals of C-MOS technology • Expected to have a very good understanding of the PD Flow for flat and hierarchal designs • Able to handle RTL/Netlist to GDSII independently at block level/SS/SoC and should have done multiple tape outs with low power implementation (Experience on floor planning, Partitioning, integration at Subsystem/Chip will be add advantage) • Should have hands-on experience of working on Lower technology nodes like 3nm, 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. • Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in block/top level signoff STA, physical verification (DRC/LVS/ERC/antenna) checks and other reliability checks(IR/EM/Xtalk) • Should have expertise on industry standard EDA tools from Synopsys , Cadence and Mentor • ( ICC2, Fusion-Compiler, Design Compiler, Primetime, PTSI, IC Validator, Innovus, Genus, Tempus, Encounter, Nanoroute, Calibre, StarRC and Redhawk, voltage storm • Exposure in DMSA flow for ECO generation and implementation. • Good knowledge of VLSI process and scripting in TCL, perl .