Job Description
This position is within the Design Technology Platform (DTP) organization of Intel Technology Development (TD) group. We are looking for a talented individual to join Test Chip Engineering (TCE) team to execute Test Chip design from early pathfinding to maturity on advanced Si technology nodes and enable diverse DE teams to contribute targeted test structures through design automation and collateral support. The team involves in the following activities: - Physical design using automation using p-cell in SKILL and python OA - QA of p-cell templates - Test structure generation using the p-cell templates - Layout analytics using ICV, Calibre EDA tools - GUI development (eg. like gpds), routing code, fill code, extraction and LVS, support Tapein environment #DesignEnablement #DesignTechnologyPlatform
Qualifications
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications - Bachelor Degree (Masters Degree preferred) in Electrical Engineering, Computer Engineering, or other related field of study. - 1 to 2 years of relevant experience in layout design or Tool Flow Methodology (TFM) development - Experience in using industry Layout editing and verification CAD tools - Strong in programming - Excellent verbal communication, technical presentation and leadership skills. Self-motivated and well organized. #designenablement #designtechnologyplatform
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.


Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.


Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.